There is known a method of building a self-test circuit for memories in a semiconductor integrated circuit and detecting a failure in a manufacturing test. This built-in self-test circuit is called a built-in self test (BIST) circuit. A built-in redundancy allocation (BIRA) circuit is known as a built-in redundant relief circuit which is used together with the BIST circuit and which performs analysis and redundant allocation on-chip.
In a semiconductor integrated circuit on which both the BIST circuit and the BIRA circuit are mounted, the BIRA circuit analyzes and processes the result of a comparison between a memory output and an expected value, and generates relief data. This relief data is then output to an external tester from the BIRA circuit. Such a semiconductor integrated circuit increases in circuit scale for the BIRA circuit mounted thereon.
Meanwhile, there has been suggested a semiconductor integrated circuit on which the BIRA circuit is not mounted and the BIST circuit is only mounted. This semiconductor integrated circuit can decrease a circuit scale because the BIRA circuit can be eliminated. However, in such a semiconductor integrated circuit, uncompressed data regarding the result of a comparison between a memory output and an expected value is serially output to a tester, and analyzed and processed in the tester. That is, a data row output by the semiconductor integrated circuit on which the BIRA circuit is not mounted is longer than a data row output by the BIRA circuit, and the number of comparisons with the expected value is greater. Thus, the test time of a memory increases.